1 - Introduction The first prototype is build for the MegaSTE. Why ? Because that's the machine I have. Once this proto works I'll work on making a STF and STE version. The goal is to first run the 68020 at the machine bus speed (8 MHz or 16MHz on a Mega STE). To make this work some 68020 signals need to be synthesized as well as some 68000 signals. I looked at a few existing cards like the LUCAS for Amiga and the Booster 020 from Jean Conter. There is also a good application note from Motorola on how to interface a 68020 with a 68000 system, which is what the ST is. The Motorola application note is AN944. So why make a new card ? ... Because I want to learn.

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2 - Current prototype The current prototype use a PGA socket for a 68020RC. It has a bunch of jumper to first make it work at the machine bus speed so no trick on the clocks and no need to resync DTACK or any signals. Once that work the next step is to have the 68020 run a constant speed, 32MHz in this case. The difficulty with the Mega STE is that it boots at 8MHz and latter on switch to 16MHz. So the cycle resync is not going to be the easiest one. If I can't get this to work, I'll at least use the same trick as the booster v2 from exxos, switch the cpu clock to 32MHz when not accessing the ST ; so when code is running from the cache, or when accessing the 32 bits address space. On the prototype I also put an expansion connector with all the signals from the 68020 so that I can then work on putting the TOS on 2x 16 bits EPROM to get a 32 bits access to the TOS.

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More progress were made this weekend. First now /DSACK1 arrives at the right time and the 68020 complete the cycle in 4 clock cycle. Before, even after delaying /AS20 it was getting DTACK to early and finishing the cycle in 3 clock cycle. This is due to the fact that the ST assert /DTACK a few ns after /AS is asserted. The ACIA access now looks good with a proper sync on E and /DSACK0 is properly asserted. I use /DSACK0 as this is what is supposed to be used for 8 bit bus access (wired to D24-D31 which is D8-D15 of the 68000 bus). Now of course .. it still doesn't work. I've notice that after the 2 first access to the ACIA... there are 2 more.. I didn't see 4 access on my test (will have to recheck) so something goes wrong here. Also I thing I use /CS2 on the Midi ACIA and then realize it was tie to VCC.. so that test is not valid. I'll have to recheck the ACIA access next week (if I can work on this next week). 2nd problem is /BG... as previously seen, when my card is on the bus, /ST_BG seem to follow /DTACK... even if I remove the jumper connecting either the CPU /BG or the ATF1504 ST_BG_OUT to the ST_BG pin ... I check with the 68000 and this doesn't happend.. so there is a problem somewhere on the card. I haven't found any shorts that would explain this. So now I need to trace all the track with a multimeter to see if I can find the issue. You can see the test setup there and there

3 - Signals resync /AS : The 68020 runs in 3 full clock cycle (6 states) as opposed to 4 (8 states) for the 68000. Motorola recommend to delay /AS by 1 bus clock cycle to align it with the standard 68000 S2 cycle. That being said, I saw that the Booster 020 doesn't do this, which mean the ST might be able to accept a 6 state cycle instead of 8. This will require testing but it can be interesting if that's the case. /DTACK to /DSACK1 : We also need to resync DTACK to DSACK1 if the CPU run at a different speed than the bus. As the Mega STE changes frequency this will requires some tricks. As said above, not sure yet how that's going to work. /BG : We need to prevent /BG to go to the ST to quickly.We will gate it on /AS to make sure we don't assert /BG to the ST if /AS is isolated from the bus (access to non ST address space or future fast TOS). /VMA and E clock: We need to synthesize these signals from the 68020 and the system clock. The Motorola application note has all the information we need. I also looked at the LUCAS code and the Booster020. I'll do a few test and keep the "best" one.

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So I spent time this week reviewing the equation, make some fix and tweak. The machine obviously boot on the TOS but crashes after 7 seconds.. which is not right as the MegaSTE with the 68000 displays the Atari logo after 4s or so. So something is not responding on the bus and the CPU keeps trying .. I guess until it gets a bus error. I checked that /VPA is asserted when accessing the ACIA (see ACIA access trace). DTACK (connected to DSACK1) also respond properly. /ST_AS is delayed by 1 half clock cycle as expected to land on S2 of the 68000 bus cycle. At this point I'm a little bit in the dark as to what is going on as the card seems to work as it boots the TOS. I used my Saleae to get proper timing as I discovered that the Open Bench logic sniffer was giving me wrong timing even when sampling at 200MHz (25 times the 8MHz bus frequency).

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This is the current MegaSTE prototype board as it was sent to the PCB house. The board should be back by the end of July (2015). I use an ATF1502 for the logic. The CPU is a MC68020RC33 PGA (fairly easy to find on eBay and cheap). The card uses a PLCC plug (Winslow W9305) to interface with the MegaSTE 68000 socket. This is somewhat hard to find and not cheap ( ~ $50 including shipping). I also added an expansion port so that I can prototype the 32 bit TOS and the SRAM.

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The PCB is now assembled. I now need to finish the CPLD coding and start the testing and debugging. There are a few jumpers as you can see. These are used to route some signals either directly to/from the 68020 to/from the 68000 socket or via the ATF1502. As the goal is to first get this working at bus speed, only some signals need to be routed to the ATF1502 to generate the "missing" 68020 signals. Once that work the jumper will allow me to route more signals to/from the 68020 and 68000 bus via the ATF1502 to try to get the CPU to run at 33MHz all the time. There might be an intermediary state where I'll use the frequency switching code from the Booster V2 to switch between 33MHz and the bus frequency.

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Weird issues We made some code changes to only use DSACK1 for all transfers (MrMartian from the Atari Age forum helped me on this) including the ACIA. So far it all looks good and the cycle are termination as they should. Now, that being said .. it still not boot. The BG issue seemed to be solved (I cleaned the PLCC socket on the mother board as there might have been some corrosion). but now we see weird pulse in the middle of a LO or HI on some signals (seen image above). We don't yet know if it's an issue with the board (interferences), issues with the ATF1504, issues with some signal from the ST (MegaSTE in this case). We see these on SIZ0 and SIZ1 which come straight from the CPU. I tested with 5 different CPU... exact same result on all of them. So I (we) need to identify where these issue are coming from (might be false signal and just a bug in the software as I enable the analog trace on the logic analyzer and the voltage is way bellow a logic 1 for TTL, CMOS or even 3.3v CMOS/TTL. So as you see, more work to do. I might have to make a new board with some inline resistor to help with signal ringing and other issues (33 ohm inline on control signal to ATF and from ATF to ST). I might try to spend more time on this card this weekend and see if we get somewhere. If not.. time for a new board with more signal cleaning options :)

I was able to run the first test in the MegaSTE. So it doesn't work .. yet. I could see some bus cycle after fixing some of the CPLD code. I think there might be a few errors in the code for the Motorola application note AN944. I was able to fix the /AS00 timing (that the /AS that goes to the mother board) and make sure it was properly delayed to match the S2 cycle. Also the AN944 equation seem to have the output of AS00 inverted, at lest it was inverted on my logic analyzer output. So there is progress and it seems to start booting as I see TOS access (/CE of ROM is triggered and match /AS00 and /DTACK). I've noticed that /BG is doing something really weird as it follows /DTACK !!! If I disconnect the cpu /BG20 signal from the mother board the signal is a steady HI for the length of my sampling but the ST_BG (so from the mother board) still shows the weird signal following /DTACK. If I put back the 68000 on the machine and sample the same signals /BG is fine. So there is something weird going on there and I need to investigate. I might have some time to do more test next weekend.

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